October 2003 1/88
ADE3000 ADE3050 ADE3100
ADE3200 ADE3250 ADE3300
LCD Display Engines
with Integrated DVI, ADC and YUV Ports
®
The ADE3xxx is a family of highly integrated display engine ICs, enabling the most advanced, flexible, and
cost-effective system-on-chip solutions for LCD display applications. The ADE3xxx line-up covers the full
range of applications from XGA analog only to dual SXGA Smart Panel designs. All twelve ADE3xxx
devices are pin-to-pin compatible and use a common software platform.
Feature Overview
■ Programmable Context Sensitive™ Scaling
■ High-quality up-scaling and down-scaling
■ Dual Input: DVI / VGA
■ Integrated 9-bit ADC/PLL
■ Integrated DVI-Rx
■ IQSync™ AutoSetup
■ Integrated programmable timing controller
■ Integrated Pattern generator
■ Perfect Picture™ Technology
■ sRGB 3D Color Warp
■ Integrated OSD
■ Advanced EMI reduction features
■ Framelock operation with Safety Mode™
■ Serial I²C interface
■ Low power 0.18 µm process technology
Product Selector
208-pin PQFP Package
Product
Input Interface Support Output Format Support
Analog DVI YUV Resolution TCON
ADE3000
xx
Up to XGA 75Hz
ADE3000T
xx
Up to XGA 75Hz
x
ADE3000SX
xx
Up to SXGA 75Hz
ADE3000SXT
xx
Up to SXGA 75Hz
x
ADE3050
xx
Up to XGA 75Hz
ADE3050T
xx
Up to XGA 75Hz
x
ADE3050SX
xx
Up to SXGA 75Hz
ADE3050SXT
xx
Up to SXGA 75Hz
x
ADE3100
xxx
Up to XGA 75Hz
ADE3200
xxx
Up to XGA 75Hz
x
ADE3250
xxx
Up to SXGA 75Hz
x
ADE3300
xxx
Up to SXGA 75Hz
ADE3XXX
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Third Generation Context Sensitive™ Scaler
● Sharper text with Edge Enhancement
● RAM based coefficients for unique
customization
● 5:1 upscale and 2:1 downscale
● Independent X - Y axis zoom and shrink
● Bob de-interlacing eliminates jaggies and
motion artifacts
Analog RGB input
● 140MHz 9-bit ADC
● Ultra low jitter digital linelock PLL
● Composite Sync and Sync on Green support
Secure DVI™ Receiver
● Single Link DVI receiver
● Input Pixel Rate from 25 to140 MHz
● Low power mode with activity detection
● Compatibility with all DVI compliant
transmitters
Digital TV Video Input
● VESA VIP 1.1, 2.0 and CCIR656 compliant
● 25 to 75 MHz input clock
IQsync™ AutoSetup
● AutoSetup configures phase, clock, level, and
position
● Supports continuous calibration for reduced
user intervention
● Detects activity on all inputs and selects the
active source
● Compatible with all standard VESA and GTF
modes
Perfect Picture™ Technology
● Video & Picture highlight zoning
● Supports up to 7 different windows
● Independent window controls for contrast
brightness, sharpness, and color
Perfect Color™ Technology
● Programmable 3D color warp
● Digital brightness, contrast, hue, and
saturation gamma controls for all inputs
● Simple white point control
● Compatible with sRGB standard
● True color dithering for 12- and 18-bit panels
● Temporal and spatial dithering
● 30-bit programmable gamma table
OSD Engine
● 256 RAM based 12x18 characters
● 1 and 4-bit per pixel color characters
● Bordering, shadowing, transparency, fade-in,
and fade-out
● Supports font rotation
● Up to 4 sub windows
● 32 entry TrueColor LUT
Programmable Timing Controller (TCON)
● Highly-programmable support for XGA, TTL
and RSDS SmartPanels
● Dual function TTL and RSDS outputs
● Advanced flicker detection and reduction
● 12 programmable timing signals for row/
column control
● Wide range of drivers & TCON compatibility
● Simulation tools for easy programming
● Supports complex polarity generation for IPS
panels
Advanced EMI Reduction Features
● Flexible data inversion / transition
minimization, single, dual, and separate
● Per pin delay, 0 to 6ns in 0.4ns increments
● Adaptive Slew Rate control outputs
● Supports 18/24/36/48-bit RSDS outputs
● Differential clock
● Spread spectrum -programmable digital FM
modulation of the output clock with no
external components
Output Format
● Supports resolutions up to SXGA @ 75Hz
● Supports 6 or 8-bit Panels
● Support double or single pixel wide formats
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ADE3XXX
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Pin Description ....................................................................................................................6
Chapter 2 ADE3XXX Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Global Control Block ..........................................................................................................13
2.2 FM Frequency Synthesizer ................................................................................................17
2.3 ADC Block ..........................................................................................................................18
2.4 Line Lock PLL Block ...........................................................................................................19
2.5 Digital Video Input (DVI) .....................................................................................................22
2.6 HDCP Block .......................................................................................................................27
2.7 YUV Block ..........................................................................................................................29
2.8 Sync Retiming Block ..........................................................................................................30
2.9 Sync Measurement Block ..................................................................................................32
2.10 Sync Mux Block ..................................................................................................................40
2.11 Data Mux Block ..................................................................................................................42
2.12 Data Measurement Block ...................................................................................................42
2.12.1 Edge Intensity ....................................................................................................................................43
2.12.2 Pixel Sum ...........................................................................................................................................43
2.12.3 Min / Max ...........................................................................................................................................43
2.12.4 PCD ...................................................................................................................................................43
2.12.5 H Position Min / Max ..........................................................................................................................43
2.12.6 V Position Min / Max ..........................................................................................................................44
2.12.7 DE Size ..............................................................................................................................................44
2.13 Programmable Nonlinearity Block ......................................................................................48
2.14 Scaler Block .......................................................................................................................49
2.15 Output Sequencer Block ....................................................................................................52
Frame Synchronization .......................................................................................................................................52
Timing Unit ..........................................................................................................................................................52
Signal Generation ...............................................................................................................................................52
2.16 Timing Controller (TCON) Block ........................................................................................55
2.17 Pattern Generator Block .....................................................................................................60
Screen Split ........................................................................................................................................................60
Pattern Engine ....................................................................................................................................................61
Borders ...............................................................................................................................................................61
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