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74F194PC

  • 74F194PC
  • 74F194PC
74F194PC
REGULATOR
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© 2000 Fairchild Semiconductor Corporation DS009498 www.fairchildsemi.com
April 1988
Revised March 2000
74F194 4-Bit Bidirectional Universal Shift Register
74F194
4-Bit Bidirectional Universal Shift Register
General Description
The 74F194 is a high-speed 4-bit bidirectional universal
shift register. As a high-speed, multifunctional, sequential
building block, it is useful in a wide variety of applications. It
may be used in serial-serial, shift left, shift right, serial-par-
allel, parallel-serial, and parallel-parallel data register
transfers.
Features
Typical shift frequency of 150 MHz
Asynchronous master reset
Hold (do nothing) mode
Fully synchronous serial or parallel data transfers
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F194SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F194SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F194PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
74F194
Unit Loading/Fan Out
Functional Description
The 74F194 contains four edge-triggered D-type flip-flops
and the necessary interstage logic to synchronously per-
form shift right, shift left, parallel load and hold operations.
Signals applied to the Select (S
0
, S
1
) inputs determine the
type of operation, as shown in the Mode Select Table. Sig-
nals on the Select, Parallel data (P
0
–P
3
) and Serial data
(D
SR
, D
SL
) inputs can change when the clock is in either
state, provided only that the recommended setup and hold
times, with respect to the clock rising edge, are observed.
A LOW signal on Master Reset (MR
) overrides all other
inputs and forces the outputs LOW.
Mode Select Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
p
n
(q
n
) = Lower case letters indicate the state of the referenced input (or
output) one setup time prior to the LOW-to-HIGH clock transition.
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
S
0
, S
1
Mode Control Inputs 1.0/1.0 20 µA/0.6 mA
P
0
–P
3
Parallel Data Inputs 1.0/1.0 20 µA/0.6 mA
D
SR
Serial Data Input (Shift Right) 1.0/1.0 20 µA/0.6 mA
D
SL
Serial Data Input (Shift Left) 1.0/1.0 20 µA/0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/0.6 mA
MR
Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
Q
0
–Q
3
Parallel Outputs 50/33.3 1 mA/20 mA
Operating Inputs Outputs
Mode MR
S
1
S
0
D
SR
D
SL
P
n
Q
0
Q
1
Q
2
Q
3
Reset L X X X X X L L L L
Hold H l l X X X q
0
q
1
q
2
q
3
Shift Left H h l X l X q
1
q
2
q
3
L
Hhl X hXq
1
q
2
q
3
H
Shift Right H l h l X X L q
0
q
1
q
2
Hlhh XXHq
0
q
1
q
2
Parallel Load H h h X X p
n
p
0
p
1
p
2
p
3
3 www.fairchildsemi.com
74F194
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias 55°C to +125°C
Junction Temperature under Bias 55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2) 0.5V to +7.0V
Input Current (Note 2) 30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output 0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
I
OH
= 1 mA
Voltage 5% V
CC
2.7 I
OH
= 1 mA
V
OL
Output LOW 10% V
CC
0.5 I
OL
= 20 mA
Voltage
I
IH
Input HIGH
5.0 µAMaxV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxV
IN
= 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current 0.6 mA Max V
IN
= 0.5V
I
OS
Output Short-Circuit Current 60 150 mA Max V
OUT
= 0V
I
CC
Power Supply Current 33 46 mA Max

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